submit news    HOME | FEEDBACK  


- Bio/Medicine

- Chemicals

- Defense

- Drug Delivery

- Education

- Electronics

- Energy

- Events

- Grants

- Industry

- Investment

- Litigation

- Materials


- Nanofabrication

- Nanoparticles

- Nanotubes

- Optics

- Partnership

- Patent

- Products

- Quantum dots

- Research

- Smart Dust

- Software

- Browse by Month

- Current Shows

- Previous Shows

- Submit Events

Become A Nanotechwire Partner

FEI Company

Veeco Instruments

Nano Science and Technology Institute

National Nanotechnology Initiative

Nanotechnology at Zyvex

Want to see your Company or Organization listed above? Become A Nanotechwire Partner Today - click here


11/8/2010 6:38:12 PM
SEMATECH Researchers to Present Breakthrough Innovations in III-V MOSFETs, FinFETs and Resistive RAMs at IEDM

Revealing research breakthroughs, engineers from SEMATECH’s Front End Processes (FEP) program will present technical papers at the 56th annual IEEE International Electron Devices Meeting (IEDM) from December 6-8, 2010, at the Hilton in San Francisco, CA.

SEMATECH experts will report on resistive RAM (RRAM) memory technologies, advanced Fin and nanowire FETs for scaled CMOS devices, high mobility III-V channel materials on 200mm silicon wafers in an industry standard MOSFET flow, and future ultra-low power tunneling FET devices — highlighting significant breakthroughs that address the growing need for higher performance and low power devices.

Additionally, SEMATECH will host invitational pre-conference workshops on December 5. The workshops will focus on technical and manufacturing gaps affecting promising emerging memory technologies and III-V channels on silicon. Co-sponsored by Tokyo Electron and Aixtron, these workshops will feature experts from industry and academia debating the challenges and opportunities in these areas in a series of presentations and panel discussions.

During the IEDM conference, SEMATECH’s FEP experts will present research results at the following sessions:

  • Session 6, Monday, Dec. 6 at 2 p.m.: Self-aligned III-V MOSFETS Heterointegrated on a 200 mm Si Substrate Using an Industry Standard Process Flow – demonstrates, for the first time, that III-V devices on silicon can be processed in a silicon pilot line with controlled contamination, uniformity and yield while demonstrating good device performance.
  • Session 16, Tuesday, Dec. 7 at 9:05 a.m.: Prospect of Tunneling Green Transistor for 0.1V CMOS – investigates tunneling green transistors for low-voltage CMOS VLSI devices and circuits. Statistical data will show that sub-60mV/decade characteristics have been clearly demonstrated on 8 inch wafers. This work is an ongoing collaboration with Prof. Chenming Hu and his co-workers at University of California Berkeley. The results of the collaborative work will be presented by Professor Hu.
  • Session 19, Tuesday, Dec. 7 at 4:25 p.m.: Metal Oxide RRAM Switching Mechanism Based on Conductive Filament Microscopic Properties – reports on critical conductive filament features controlling RRAM operations. The forming process is found to define the filament shape, which determines the temperature profile and, consequently, switching characteristics.
  • Session 26, Wednesday, Dec. 8 at 9:55 a.m.: Contact Resistance Reduction to FinFET Source/Drain Using Dielectric Dipole Mitigated Schottky Barrier Height Tuning – shows, for the first time, a contact resistance reduction using dielectric dipole mitigated Schottky barrier height tuning on a FinFET source. This technique is very promising for emerging devices, alternative channel materials, and sub-22nm CMOSFETs, where the Schottky barrier height and resulting higher parasitic contact resistance are significant barriers for scaling.
  • Session 34, Wednesday, Dec. 8 at 2 p.m.: Strained SiGe and Si FinFETs for High Performance Logic with SiGe/Si Stack on SOI – reports on a dual channel scheme for high mobility CMOS FinFETs.

The IEDM conference draws an international audience of industry professionals for an intensive exploration of design, manufacturing, physics, and modeling of semiconductors and other electronic devices. The conference spotlights leading work from the world’s top electronics scientists and engineers; it is one of many industry forums SEMATECH uses to collaborate with scientists and engineers from corporations, universities, and other research institutions, many of whom are research partners.


For over 20 years, SEMATECH, the global consortium of leading semiconductor manufacturers, has set global direction, enabled flexible collaboration, and bridged strategic R&D; to manufacturing. Today, we continue accelerating the next technology revolution with our nanoelectronics and emerging technology partners.

Other Headlines from SEMATECH ...
 - FUJIFILM Joins SEMATECH’s Resist Center for Advanced EUV Resist Development at UAlbany NanoCollege
 - TSMC Joins SEMATECH to Accelerate Semiconductor Technology Development
 - U.S. Department of Energy Awards Funding to CNSE CIGS Solar Project
 - In major victory, Schumer announces CNSE-SEMATECH big winner of high-tech grant that will make Albany a national center in solar cell research and create thousands of jobs
 - SEMATECH Reports Advances in Bond Process for 3D Integration Development

More Events Headlines ...
 - Free Keithley Web-Based Seminar Addresses High Brightness LED Test Techniques
 - Leading UK Nano Organisations lend support for NANO Live UK 2011
 - Asylum Research Announces UK User Meeting and Forum June 21, 2011 in Edinburgh
 - CEA-Leti to Present 2 Invited Papers at May 23-26 Conference on Frontiers of Characterization and Metrology for Nanoelectronics
 - UAlbany NanoCollege to host prestigious International Nanotechnology Conference on Communication and Cooperation

« Back To List »

- submit company
- submit news
- submit events
- advertise here

- More Events

Copyright © 2017 | Privacy Policy |