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9/18/2004 10:58:00 PM
Nano memory scheme handles defects

Electrical components that are two or three orders of magnitude smaller than E. coli bacteria promise ultra-high speed at ultra-low-power, but they also present several challenges. Nanoscale electronics devices have a fairly high defect rate, and architectures designed to guide their use must take this into account

Researchers from Hongik University in Korea have devised a memory architecture designed for nanoscale crossbar electronics.

The technique addresses the problem of defects in molecular memory without significantly disrupting existing molecular memory architectures such as that demonstrated by Hewlett-Packard labs, according to the researchers.

Key to the architecture is a traditional layer of electronics that keeps track of defects and performs address translation in order to work around the defects in the molecular part of a chip.

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